As basic algorithms of decoding an LDPC code, there are a “Sum-Product algorithm” and a “Min-Sum algorithm”. According to these algorithms, the decoding is performed while repeatedly calculating a likelihood ratio (LLR) as probabilistic reliability information of a reception signal (see Nonpatent Document 1). The “Sum-Product algorithm” has high decoding performance, but has high calculation cost for packaging such as the need for holding a table, because a calculation using a mathematical function is required. At least a memory that stores intermediate values by only the number of “1” contained in a binary check matrix of “0” and “1” is necessary. On the other hand, the “Min-Sum algorithm” does not require a mathematical function, and has small calculation cost, but decoding performance is degraded.
The “Sum-Product algorithm” is explained. First, at the transmitter side, transmission data is LDPC encoded using a parity check matrix H of M rows×N columns, and a codeword c=(c1, c2, . . . , cN), cn=0, 1 (n=1, 2, . . . , N). A modulation such as a BPSK (Binary Phase Shift Keying) modulation is performed to this codeword c, and a modulation signal x=(x1, x2, . . . , xN) is sent.
On the other hand, the receiver side receives, via an Additive White Gaussian Noise Channel (AWGN channel), a signal y=(y1, y2, . . . , yN) as expressed by the following Equation (1):yn=xn+en  (1)where en is a Gaussian noise series of which average is 0, and a variance σ2=N0/2.
At the receiver side, a predetermined digital demodulation corresponding to the above BPSK modulation is performed to the modulation signal received via the above channel. Further, iterative decoding by the “Sum-Product algorithm” is executed to a logarithmic likelihood ratio (LLR) obtained from the demodulation result, and a hard decision result is finally output.
A conventional decoding method “Sum-Product algorithm” implemented by the above receiver is shown below.
(Initialization Step)
First, the number of repetitions l=1 and the maximum number of repetitions lmax are set, and, as LLR: βmn(l=1) from a bit node to a check node at the initial time, a reception LLR: λn is input as given by the following Equation (2):βmn(l)=λn n=1, 2, . . . , Nm=1, 2, . . . , M  (2)
(Row Processing Step)
Next, as row processing, LLR: αmn(l) at the first repetition (repetition first-time LLR: αmn(l)) of a bit n to be sent from the check node m to the bit node n is updated for each m and n by the following Equation (3):
                    [Expression  1]                                                                      α                      m            ⁢                                                  ⁢            n                                (            1            )                          =                  2          ⁢                                          ⁢                                    tanh                              -                1                                      (                                          ∏                                                      n                    ′                                    ∈                                                            N                      ⁡                                              (                        m                        )                                                              ⁢                    \                    ⁢                                                                                  ⁢                    n                                                              ⁢                              tanh                (                                                      β                                          mn                      ′                                                              (                                              1                        -                        1                                            )                                                        2                                )                                      )                                              (        3        )            
where N(m) is a set of column numbers having “1” of a m-th row, n′ is N(m) other than n, and βmn(l−1) is LLR from the (l−1)-th bit node to the check node other than an n-th column.
(Column Processing Step)
Next, as a column processing, a repetition first-time LLR: βmn(l) of a bit n to be sent from the bit node n to the check node m is updated for each m and n by the following Equation (4):
                    [Expression  2]                                                                      β          mn                      (            1            )                          =                              λ            n                    +                                    ∑                                                m                  ′                                ∈                                                      M                    ⁡                                          (                      n                      )                                                        ⁢                  \                  ⁢                                                                          ⁢                  m                                                      ⁢                          α                                                m                  ′                                ⁢                n                                            (                1                )                                                                        (        4        )            
A repetition first-time posterior value βn(l) of a bit n for a hard decision is updated for each n by the following Equation (5):
                    [Expression  3]                                                                      β          n                      (            1            )                          =                              λ            n                    +                                    ∑                                                m                  ′                                ∈                                  M                  ⁡                                      (                    n                    )                                                                        ⁢                          α              n                              (                1                )                                                                        (        5        )            
where M(n) is a set of row numbers having “1” of an n-th column, m′ is M(n) other than m, and βm′n(l) is LLR from the first check node to the bit node other than an m-th row.
(Stop Regulation)
Thereafter, when the repetition first-time posterior value βn(l) of the bit n is “βn(l)>0”, a decoding result is “xn′=1” (where x′ corresponds to the original transmission signal x). On the other hand, when “βn(l)≦0”, a decoding result is “xn′=0”, and a decoding result x′=(x1′, x2′, . . . , XN′) is obtained.
When a result of parity check is “Hx′=0” or when the number of repetitions is “l=1max” (when any one of these condition is satisfied), a decoding result x′ in this case is output. When none of the two conditions is satisfied, “l=l+1” is set, and the process control returns to the above row processing. Thereafter, the calculation is sequentially performed.
Nonpatent Document 1: Low-Density Parity-Check Codes and Its Decoding Algorithm, LDPC (Low Density Parity Check) code/sum-product decoding algorithm, Tadashi Wadayama, Triceps.